This invention relates to circuits and methods for monitoring phase error between two signals and, more particularly, to such monitoring in which the phase error between the signals is subject to phase error modulation.
AC electric power systems are usually connected in parallel to increase total system rating or in certain cases such as airborne power systems, to increase reliability. One well known type of aircraft electric power system is the DC link variable speed constant frequency (VSCF) system. Such systems include a plurality of power pole switching elements which synthesize an AC output by switching current from a pair of DC link conductors in a fixed switching pattern, which may be generated by a microprocessor or other digital circuit. When these systems are to be operated in parallel with each other or with another source such as a ground power cart, each of the power sources must be synchronized. Since DC link VSCF systems are clock-based, a master clock signal is used to synchronize each of the system channels.
The clock signal is a common signal used to synchronize each channel. No break power transfer (NBPT) is a special application of a parallel system which allows momentary paralleling with another power source. The other source is typically an auxiliary power unit (APU) or a ground power unit (GPU). For NBPT, the master clock should be able to track the frequency of an external source. During NBPT, there is a transient due to mismatched phase angles and magnitudes of the two system voltages about to be momentarily parallelled. Severe transients and tripping of the VSCF system could result if excessive phase error exists prior to NBPT. To minimize such transients, it is necessary to ensure proper phase angle matching prior to paralleling.
In a typical system, a phase error signal is produced, which contains a pulse train with the phase error indicated by the pulse widths. External power sources often have a frequency modulation specification which permits a certain amount of frequency modulation in the output. VSCF paralleling controls typically have a phase locked loop (PLL). This PLL provides a frequency reference (master clock), which is phase locked with the external power source frequency, to all VSCF channels. The phase error is the phase difference between the external power source frequency and the master clock reference for the VSCF system. If the external power source is subject to frequency modulation, the PLL will be continuously in a state of change, trying to track the external frequency. The phase error will consequently also be in a continuous state of change.
The PLL is a closed loop system and has a transient response associated with it such that any frequency changes in the external power source frequency are reflected in the master clock after a time delay. For example, if the external power source frequency is changed by 10 Hz (from 400 Hz to 410 Hz), the phase error will increase, resulting in a change in the frequency of the master clock and as the master clock frequency reaches the external power source frequency, the phase error will reduce to zero. So on a transient basis, the phase error may exceed the specified static limit for parallelability. Therefore, a check of the average dynamic phase error between the external source and the VSCF system will be required to determine if the systems can be paralleled. This invention detects and extracts the average dynamic phase error, to determine if it is within certain predetermined specifications.